View COIC5130A_1120705.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

introduction the COIC5130A contains both a high data rate programmable reed-solomon encoder and a separate decoder that will process blocks of up to 255 eight bit symbols to provide corrections (t) of up to 10 errors per code block at data rates up to 320 mbs. the encoder output code block will contain the unaltered original data symbols followed by the generated parity symbols. the decoder input will contain the received data symbols including errors that may be introduced during transmission. decoder output will be a completely corrected block or will be marked as non-correctable and the block will be outputted as received without any changes. the encoder and decoder can be operated independent of each other. either or both may active at one time. as the devices have separate clocks, the encoder and decoder may operate at different data rates. the 128-pin mqfp device is manufactured using an 0.5micron cmos technology by a iso 9000 certified facility. this part is functionally compatible with the coic5125a, coic5126a, coic5127a and coic5128a and also the ampex 1295125-01 and 1295126, but includes features not found in the ampex devices. co optic ~ ~ 1742 sand hill road, suite 303, palo alto, ca 94304 n tel: (650)321-3390 n fax: (650) 322-8569 n email: sales@co-optic.com n we b : www.co-optic.com ?998, co-optic, inc. all rights reserved. specifications subject to change without notice. COIC5130A specifications t = 0 to 10, 320mbs, programmable reed-solomon error correction encoder and decoder for information on separate encoder refer to the coic5127a data sheet. for information on separate decoder refer to the coic5128a data sheet. preliminary device specification
encoder functional description the COIC5130A contains an encoder that will provide ( n, n-r ) reed- solomon forward error correction encoding of blocks of eight bit sym- bols. the number of parity symbols ( r ) may be from 0 to 20 , 0 in pass through mode, and the number of symbols in a block ( n ) from r+1 to 255. at the decoder two parity bytes will be used for each untagged symbol error correction and one parity byte used for a location identi- fied error (erasure ) correction. this will provide correction of up to 10 errors ( e ) or up to 20 erasures ( e ) or a combination as long as 2e + e COIC5130A specifications co optic ~ ~ 2 encoder control clock reset trien t (3.0) en out en out din (7.0) dout (7.0) rty 1 0 1 0
COIC5130A specifications co optic ~ ~ 3 the number of data symbols ( k ) of succeeding blocks can be changed as desired at any time. this will change the code rate for the blocks, but to change the correction power ( r ) the section must be re-initialized. this can also be done at any time, but any blocks in process at that time will be lost. encoder duplex operation half duplex operation can be achieved on a single bi-directional chan- nel at a maximum transmission rate equal toone half of the symbol clock. allowing for transmission and circuit switching delays, data can be switched from the unit encoder to the decoder on any symbol boundary. external data switching and control circuits will be required to control data flow and device enables. full duplex at full clock rate can be implemented but requires two data carriers or echo cancellation. encoder pass through mode any number of symbols can be passed through the encoder without any encoding if the enable in (enlna) is held high and enable out ( enouta) is held low while the symbols are clocked into the section. this will allow the maximum data transfer rate, but will not provide any error correction (t=0 ). to end pass through mode operation enlna must be brought high, which will start the encoding process. this must be at the beginning of a block for correct operations. pass through mode may be invoked at any time but any blocks in process when this mode is start- ed will not be encoded properly and will not be able to be decoded. decoder functional description COIC5130A includes a high data rate programmable forward error correction devices that can decode reed-solomon code blocks of up to 255 eight bit data symbols. it provides corrections of up to 10 symbol errors per block at data rates up to 320 mbs. blocks with more errors than are correctable are so flagged with data outputted as received ( no corrections ). note: blocks must contain at least 8 parity symbols, except when operating in bypass mode. the decoder input code block will contain the transmitted data and par- ity symbols, including corruption by channel noise ( errors ). a symbol error is corrected the same regardless of the number of incorrect bits in the symbol and decoding time is the same regardless of the number of errors in a block. decoder output data will be corrected data plus cor- rected parity or block error data. error location and correction data is also provided. no clock other than the data clock is required. input and output are one byte per clock cycle. COIC5130A uses the primitive polynomial px = x 8 + x4 + x 3 + x2 + x0 which complies with smpte d-1 / d-2 digital video standards, dvb,dbs, davic, dsl, ansi id-1 / id-2, and mil std 2179a. the COIC5130A is functionally compatible with the coic5127 encoder and coic5128 decoder as well as the t=5 ampex 1295126-01. it includes features not found in that device, and using r = 20 corrects up to 10 errors per block. r-1 devices use the generator polynomial : g ( x) = ?( x - i ) i=0 decoder functional block diagram decoder features ? supports 8 bit symbol reed solomon codes ( n, n-r ) with 0 < r < 20 and n < 255, n= symbols per block including parity, r = number of parity symbols (note: r is often called 2t) ? corrects up to 10 errors per block ? coic5128a has 3 selectable latencies: default ( ampex / aha ) = 2n + 5r + 33 clock cycles with a minimum block length of 5r + 15 latency 1 = 2n + 2r + 13 clock cycles with a minimum block length of 2r + 13 latency 2 = 3n /2 +3r/2 + 15 clock cycles with a minimum block length of 3r/2 + 15 ? contains complete decoder device. no external memory or control required after initialization ? data rates up to 40 mbs ( 320 mbs ) with 0 to 40 mhz symbol clock ? end of block flag eases applications ? input and output data are at the identical rate and operates on data clock only ? provides pass through mode ( no correction ) switching on-the-fly ? latency is constant regardless of error patterns ? allows code rate change ( less data, same parity ) on-the-fly error locator & evaluator fifo din7 - din0 clk dataen enabin reset staten short1 p0 - p4 error correct dout7- dout0 mag7- mag0 loc datardy corr control short2
COIC5130A specifications co optic ~ ~ 4 ? provides complete error location and correction information ? flags uncorrectable blocks ? 4.5 to 5.5 volt operation ? -40 to + 85 degrees c operation range (extended range available) ? iso 9000 certified manufacturing decoder functional description the device contains a decoder that will provide ( n, n-r ) reed-solomon forward error correction decoding of blocks of eight bit symbols. the number of parity symbols (r ) may be from 8 to 20, 0 in pass through mode, and the number of symbols in a block ( n ) up to 255 . two par- ity bytes will be used for each symbol error correction. this device will provide correction of up to 10 symbol errors ( e ) as long as 2e COIC5130A allows three different equations to determine the mini- mum block lengths.when pin 16 is low and pin 9 low or nc the default equation is minimum block length = 5r + 15 bytes.when pin 9 is held at high and pin 16 is low level latency1 is invoked and the minimum block length equation is changed to (2r + 13) bytes. if pin 16 is high latency 2 is invoked and the minimum block length is 3r/2 + 15 regar- dles of the level of pin 9. decoder latency the time that is required for the data to flow through the device is called latency and is measured in symbol clock cycles. the devices can be operated with any of three latencies, under the control of oplan1,pin 9 and oplan2, pin 16. latencies are a function of the block length and correction level, but unaffected by error patterns. the default latency (pin 9 and 16 both low) is equal to 2n + 5r + 33 symbol clock cycles,
COIC5130A specifications co optic ~ ~ 5 which is compatible with the ampex 1295126-01 device. when pin 9 is held to high level and pin 16 is low latency 1 is invoked and the equa- tion is changed to 2n +2r + 13 symbol clock cycles. latency 2 is involked if pin 16 is high regardless of the level of pin 9 and the equa- tion is 3n/2 +3r/2 +15. effects of optional shorter latency and mini- mum code length ( optln ) : the combination of the shorter code and latency can result in considerable increase in effective data transfer. in most new designs the latency1 or latency 2 option will provide the best operations. example: if a desired code is ( 64,48 ) r= 16, the default minimum block length ( 5r + 33 ) is 95 bytes which requires 31 " filler " bytes to be inserted in each block., a loss of over 33 % of the channel effectiveness. the latency ( 2n+5r+33 ) is 313 clock cycles. with optln2 invoked the minimum block length is 39 bytes , which does not require any filler bytes so there is no loss of channel effectiveness. the latency is 135 clock cycles. decoding after the COIC5130A is initialized it can begin decoding incoming blocks. it is a good idea, but not absolutely necessary, to pass at least as many dummy symbols as the latency through the device before actual data is used in order to clear out any spurious information in the unit. although it is not recommended, block of data can be used to initialize the device can be made up of valid data, if step one has been complet- ed. to decode, the enabln is brought high and held high throughout the decoding secession. at the beginning of a code block dataen is brought high at the leading edge of the first symbol clock pulse and held high while the data symbols are being clocked into the device, that is n-r symbol clock pluses. dataen is brought low with the first parity symbol and held low for r symbol clock cycles while the parity symbols are clocked into the decoder. dataen? going highagain marks the end of parity and the start of the next block. the first data symbol is placed on the dout bus, the datrdy line will go high and the unit will begin to output data symbols when the number of symbol clocks required for processing latency are complete. at the end of n-r symbols the datrdy line goes low and parity symbols are outputted correct correct pin --- goes high as the block starts being outputted if the block contains corrected symbols or low if the block is outputted as it was received due to either 0 or more than r errors in the block. uncorr if the block cannot be corrected uncorr, pin --- will go to the high level. this will occurr as the block being processed starts to be outputted. staten if staten has been set high the first two parity bytes will be replaced with error information. byte 1 will show fxxeeeee and byte 2 will show fxxttttt where: f = block not correctable if high, block was corrected if low. eeeee = erasure count will be 0. ttttt = total number of corrections made in the block. if the block was not correctable ( f bit is high ) e and t values will be meaningless. if staten is low all of the corrected parity symbols will be clocked out of the decoder. decoder error information output in order to help optimize the application ecc function, detailed error information for each block is also available while the decoder data out- put is in process. it is not necessary to use this information for proper operation the part. if the symbol being outputed from the decoder has been corrected erloc (pin 24) will go high. the pattern used to correct that symbol will apprear on cmag 0 -cmag7 pins at the same time. note that the error is actually the logical inverse of the correction. (the user must provide external storage and processing of this information as the coic5130 does not store these error location or correction information outputs. if the decoder detects more than r/2 errors erloc will remain low throughout the block as no changes will be made. the uncorr line or status bytes must be monitored to flag this condition. decoder pass through mode ( r =0 ) any number of symbols can be passed through the decoder without any changes (corrections) if the enable in ( enabln ) is held low while sym- bols are clocked into the device. the input symbols, data and parity if any, will be passed unchanged to the output ( dout ) after the number of symbol clocks needed for processing latency. in this mode there will normally not be any parity symbols. that will allow transfer of data symbols at the maximum rate, but will not provide any error correction (t=0). to end pass through mode operation enabln must be brought high, which will start the decoding process. this must be at the beginning of a block for correct operations. pass through mode may be invoked at any time but any blocks in process when this mode is started will not be decoded properly. enobk when the last byte of a block is outputted enobk pin 22 will go to the high level for one clock period.
COIC5130A specifications co optic ~ ~ 6 encoder output timing clock t ckr t ckw t ckf t ck t isu t ih t sd t ckw input output decoder output timing clock t ckr t ckw t ckf t ck t isu t ih t sd t ckw input output encoder initialization before operation the encoder must be initialized to define the number of parity symbols (r). to initialize the binary value of r/2, (0 to 10) is placed in t0 ? t3 ( t0 is least significant ) while reset and enin are held low for four sym- bol clock periods. reset is then brought high for two symbol clock periods. the inputs on t0 ? t3 can then be released and the encoder can start normal operation. any tx pin that is not used must be held low or connected to ground. decoder initialization certain architectural and mathematical properties of this device are not hard wired and must be set up during the initialization control sequence. these properties include: 1. the overall message block length (n) 2. the number of data bytes (k) 3. the total number of check bytes (r) 4. the number of check bytes allocated for correction only ( p ) 5. whether the first check byte output positions are used for status bytes or check bytes ( staten ) 6. whether to use ampex compatible, non-compatible, or short timing ( short1 , short2 )
COIC5130A specifications co optic ~ ~ 7 these properties must be initialized before normal operation can begin. there are two distinct phases of the initialization proce ss. in phase one, the values of p , staten and short1 and short2 are initialized. in phase two, the first message block through the device is used to set the valuesof n , k and r . the phase one sequence consists of at least 4 clock cycles in which reset is held low followed by at least 2 clock cycles during which reset is held high. reset must then remain high for all subsequent operations or else an unwanted initialization sequence will ensue. the desired values of staten and p4 - p0 must be maintained during the first phase of initialization. the desired value of short1 and short2 must be maintained during all the phases of operation of the device. dataen must be held low during the entire six clock sequence or unintended processing of spurious messages may occur. decoder initialization control sequence timing the rising edge of dataen at the end of the phase one initialization sequence marks the beginning of the first message block, which is the beginning of phase two of the initialization process. dataen has the role of initializing the parameters of n, k and r. dataen has a dif- ferent function on all subsequent blocks until an initialization sequence is begun once again. as the first message block passes through the device, dataen is held high for k clock cycles and then low for r clock cycles. dataen going high again marks the first byte of the sec- ond block and implies the end of the phase two initialization sequence. dataen has thus defined r, k and n for all subsequent blocks until another initialization sequence is performed. decoder message input timing din7 - din0 dataen enabin k data bytes r parity bytes p4-p0 reset at least 4 clock cycles at least 2 clock cycles initialization message staten dataen enabin
COIC5130A specifications co optic ~ ~ 8 message decoding during message decoding the device clocks in the encoded message block from the din7 - din0 input bus on the rising edge of clk .the device then computes polynomials for this data using a high performance reed-solomon coding algorithm, and then proceeds to use the calculated polynomials to correct any errors, if possible. these polynomials are a series of complex equations that will indicate n ot only the position of incorrect bytes but will also produce the necessary information to correct them. the timing of the decoding operation is defined decoder message output timing dout7 - dout0 datardy corr k data bytes r parity bytes the action taken by the decoder with respect to a given message block is determined in all cases by the quantity of errors recei ved. the device reports its action via the corr output pin. if p = r, a high output on the corr pin indicates that the message block being output is correct.a low output indicates that a correction was not performed because there were too many errors or no errors. in situat ions where p has been chosen to be not equal to r, the meaning of the uncorr pin is that more than p/2 errors have occurred. decoder optional status bytes the optional status bytes, that may be output at the end of the message block, indicate the number of errors encountered and may be used to determine the exact meaning of the corr output when p r. the first status byte has all of its bits set low except bit 7, which is the ca (correction attempted) flag. the ca flag goes low when e r/2 (the message block was successfully decoded). therefore, anytime ca is high, the message block should be retransmitted since there were probably too many errors to reliably correct.also, if p = r th en ca will always be low when the corr output pin is high and high when corr is low. in the second status byte, bits 4 through o are a binary count of the number of errors encountered. bit 4 is most significant. the r emaining bits are always low.
1 nc n/a no connection 2 dec_mag0 decoder error magnitude 0. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 3 nc n/a no connection 4 dec_mag1 decoder error magnitude 1. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 5 nc n/a no connection 6 dec_mag2 decoder error magnitude 2. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 7 dec_dout6 decoder data output bit 6. bit 7 is msb. output 8v dd n/a +5 volt power power 9 dec_dout5 decoder data output bit 5. bit 7 is msb. output 10 nc n/a no connection 11 gnd n/a ground power 12 nc n/a no connection 13 dec_dout4 decoder data output bit 4. bit 7 is msb. output 14 nc n/a no connection 15 dec_dout3 decoder data output bit 3. bit 7 is msb. output 16 nc n/a no connection 17 v dd n/a +5 volt power power 18 dec_dout2 decoder data output bit 2. bit 7 is msb. output 19 dec_dout1 decoder data output bit 1. bit 7 is msb. output 20 gnd n/a ground power 21 nc n/a no connection COIC5130A specifications co optic ~ ~ 9 table 1: device pinout pinout pin# signal name encoder / description decoder signal type
table 1: device pinout, continued COIC5130A specifications co optic ~ ~ 10 pin# signal name encoder / description decoder signal type 22 dec_dout0 decoder data output bit 0. bit 7 is msb. output 23 gnd n/a ground power 24 dec_datardy decoder data ready. assertive high. this output is held high for data bytes and low check bytes. output 25 dec_mag3 decoder error magnitude 3. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 26 nc n/a no connection 27 dec_mag4 decoder error magnitude 4. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 28 nc n/a no connection 29 nc n/a no connection 30 dec_mag5 decoder error magnitude 5. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 31 nc n/a no connection 32 nc n/a no connection 33 nc n/a no connection 34 nc n/a no connection 35 v dd n/a +5 volt power power 36 enc_test_se encoder foundry test pin - do not use 37 gnd n/a ground 38 gnd n/a ground 39 dec_mag6 decoder error magnitude 6. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 40 dec_staten decoder status enable. asservie high. if this signal is high during reset then the decoder will be programmed to output two status bytes with each message block. input
table 1: device pinout, continued COIC5130A specifications co optic ~ ~ 11 pin# signal name encoder / description decoder signal type 41 nc n/a no connection 42 dec_mag7 decoder error magnitude 7. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. ttl output 43 v dd n/a +5 volt power power 44 dec_din7 decoder decoder symbol input bit 7. bit 7 is msb. input 45 enc_test_si encoder foundry test pin - do not use 46 dec_din6 decoder decoder symbol input bit 6. bit 7 is msb. input 47 gnd n/a ground power 48 enc_dout6 encoder encoder data output bit 6 tristate 49 v dd n/a +5 volt power power 50 enc_din6 encoder encoder data input bit 6 input 51 dec_test_si decoder foundry test pin - do not use 52 v dd n/a +5 volt power power 53 dec_din5 decoder decoder symbol input bit 5. bit 7 is msb. input 54 enc_din7 decoder encoder data input bit 7 input 55 gnd n/a ground power 56 enc_dout7 encoder encoder data output bit 7 tristate 57 v dd n/a +5 volt power power 58 gnd n/a ground 59 dec_din4 decoder decoder symbol input bit 4. bit 7 is msb. input 60 enc_dout4 encoder encoder data output bit 4 tristate 61 dec_din3 decoder decoder symbol input bit 3. bit 7 is msb. input 62 nc n/a no connection 63 enc_din4 encoder encoder data input bit 4 input
table 1: device pinout, continued COIC5130A specifications co optic ~ ~ 12 pin# signal name encoder / description decoder signal type 64 nc n/a no connection 65 dec_uncorr decoder decoder uncorrectable block. assertive high. indicates message block contains uncorrectable errors. output 66 v dd n/a +5 volt power power 67 enc_din5 encoder encoder data input bit 5 input 68 enc_dout5 encoder encoder data output bit 5 tristate 69 gnd n/a ground power 70 dec_din2 decoder decoder symbol input bit 2. bit 7 is msb. input 71 enc_rdy encoder indicates data symbols are on the encoder enc_dout bus output 72 dec_din1 decoder decoder symbol input bit 1. bit 7 is msb. input 73 enc_enout encoder enables encoder din bus onto the dout bus input 74 v dd n/a +5 volt power 75 enc_enin encoder enable encoder din bus into the parity generator input 76 dec_din0 decoder decoder symbol input bit 0. bit 7 is msb. input 77 enc_reset encoder initializes encoder into a know state (high) input 78 gnd n/a ground power 79 enc_trien encoder tri-states the encoder enc_dout bus drivers when high input 80 dec_daten decoder decoder data enable. assertive high. this input is used to signal the difference between data bytes and check bytes. input 81 dec_enabin decoder "decoder enable data correction. assertive high. when this input is asserted, the device performs corrections on the message block. when cen is low, the device does not perform corrections but continues to report status is initialized to do so." input 82 enc_clock encoder encoder master and symbol clock. input 83 enc_ta2 encoder bit 2 of the encoder t select bus input 84 v dd n/a +5 volt power power 85 enc_ta1 encoder bit 1 of the encoder t select bus input
COIC5130A specifications co optic ~ ~ 13 pin# signal name encoder / description decoder signal type 86 dec_p3 decoder decoder parity input bit 3. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 87 enc_ta0 encoder bit 0 of the encoder t select bus input 88 dec_p2 decoder decoder parity input bit 2. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 89 vdd n/a +5 volt power power 90 dec_p1 decoder decoder parity input bit 1. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 91 enc_din3 encoder encoder data input bit 3 input 92 dec_p4 decoder decoder parity input bit 4. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 93 enc_dout3 encoder encoder data output bit 3 tristate 94 enc_ta3 encoder bit 3 of the encoder t select bus input 95 dec_short2 decoder decoder latency select 2. selects latency according to table 2: latency and minimum block size selection. input 96 nc n/a no connection 97 enc_dout2 encoder encoder data output bit 2 tristate 98 nc n/a no connection 99 enc_din2 encoder encoder data input bit 2 input 100 nc n/a no connection 101 vdd n/a +5 volt power power 102 dec_reset decoder decoder system reset. assertive low. reset timing is critical to the initialization of the device input 103 enc_din1 encoder encoder data input bit 1 input 104 vdd n/a +5 volt power power 105 enc_dout1 encoder encoder data output bit 1 tristate table 1: device pinout, continued
COIC5130A specifications co optic ~ ~ 14 pin# signal name encoder / description decoder signal type 106 gnd n/a ground power 107 nc n/a no connection 108 dec_test_so decoder foundry test pin - do not use 109 gnd n/a ground power 110 dec_short1 decoder decoder latency select 1. selects latency according to table 2: latency and minimum block size selection. input 111 enc_dout0 encoder encoder data output bit 0 tristate 112 gnd n/a ground power 113 enc_din0 encoder encoder data input bit 0 input 114 v dd n/a +5 volt power power 115 dec_test_se decoder foundry test pin - do not use 116 enc_test_so encoder foundry test pin - do not use 117 dec_clock decoder decoder master clock. all inputs and outputs are synchronized by the rising edge of dec_clock. input 118 gnd n/a ground power 119 dec_corr decoder decoder message block corrected. assertive high. indicates that errors have been found and corrected in message block. output 120 dec_eob decoder decoder end of block. 1/0 = end/not end of block. output 121 nc n/a no connection 122 dec_dout7 decoder data output bit 7. bit 7 is msb. output 123 dec_loc decoder decoder error location. assertive high. this output goes high if the current symbol outout on q7-q0 has had a correction applied to it. output 124 v dd n/a +5 volt power power 125 nc n/a no connection 126 gnd n/a ground power 127 nc n/a no connection 128 v dd n/a +5 volt power power table 1: device pinout, continued
15 COIC5130A specifications co optic ~ ~ decoder input pins pin# signal description signal type 76 dec_din0 decoder symbol input bit 0. bit 7 is msb. input 72 dec_din1 decoder symbol input bit 1. bit 7 is msb. input 70 dec_din2 decoder symbol input bit 2. bit 7 is msb. input 61 dec_din3 decoder symbol input bit 3. bit 7 is msb. input 59 dec_din4 decoder symbol input bit 4. bit 7 is msb. input 53 dec_din5 decoder symbol input bit 5. bit 7 is msb. input 46 dec_din6 decoder symbol input bit 6. bit 7 is msb. input 44 dec_din7 decoder symbol input bit 7. bit 7 is msb. input pinout decoder output pins pin# signal description signal type 22 dec_dout0 data output bit 0. bit 7 is msb. output 19 dec_dout1 data output bit 1. bit 7 is msb. output 18 dec_dout2 data output bit 2. bit 7 is msb. output 15 dec_dout3 data output bit 3. bit 7 is msb. output 13 dec_dout4 data output bit 4. bit 7 is msb. output 9 dec_dout5 data output bit 5. bit 7 is msb. output 7 dec_dout6 data output bit 6. bit 7 is msb. output 122 dec_dout7 data output bit 7. bit 7 is msb. output decoder error magnitude pins pin# signal description signal type 2 dec_mag0 error magnitude 0. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 4 dec_mag1 error magnitude 1. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output
16 COIC5130A specifications co optic ~ ~ decoder error magnitude pins, continued pin# signal description signal type 6 dec_mag2 error magnitude 2. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 25 dec_mag3 error magnitude 3. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 27 dec_mag4 error magnitude 4. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 30 dec_mag5 error magnitude 5. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 39 dec_mag6 error magnitude 6. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 42 dec_mag7 error magnitude 7. this output indicates which bit of the current symbol output on q7-q0 has been corrected when loc is high. this output is indeterminate and should be ignored when loc is low. output 90 dec_p1 decoder parity input bit 1. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 88 dec_p2 decoder parity input bit 2. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 86 dec_p3 decoder parity input bit 3. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input 92 dec_p4 decoder parity input bit 4. this determines the value of (p) which is the maximum of check bytes that the device will use in correction before flagging the block as uncorrectable. normally set to the # of check bytes (r). p4 is the most significant bits. input decoder parity input pins pin# signal description signal type decoder latency select pins pin# signal description signal type 110 dec_short1 decoder latency select 1. selects latency according to table 2: latency and minimum block size selection. input 95 dec_short2 decoder latency select 2. selects latency according to table 2: latency and minimum block size selection. input
117 dec_clock decoder master clock. all inputs and outputs are synchronized by the rising edge of dec_clock. input 119 dec_corr decoder message block corrected. assertive high. indicates that errors have been found and corrected in message block. output 24 dec_datardy data ready. assertive high. this output is held high for data bytes and low check bytes. output 80 dec_daten decoder data enable. assertive high. this input is used to signal the difference between data bytes and check bytes. input 81 dec_enabin decoder enable data correction. assertive high. when this input is asserted, the device performs corrections on the message block. when cen is low, the device does not perform corrections but continues to report status is initialized to do so. input 120 dec_eob decoder end of block. 1/0 = end/not end of block. output 123 dec_loc decoder error location. assertive high. this output goes high if the current symbol outout on q7-q0 has had a correction applied to it. output 102 dec_reset decoder system reset. assertive low. reset timing is critical to the initialization of the device. input 40 dec_staten status enable. asservie high. if this signal is high during reset then the decoder will be programmed to output two status bytes with each message block. input 65 dec_uncorr decoder uncorrectable block. assertive high. indicates message block contains uncorrectable errors. output COIC5130A specifications co optic ~ ~ 17 encoder data input pins pin# signal description signal type 113 enc_din0 encoder data input bit 0. input 103 enc_din1 encoder data input bit 1. input 99 enc_din2 encoder data input bit 2. input 91 enc_din3 encoder data input bit 3. input 63 enc_din4 encoder data input bit 4. input 67 enc_din5 encoder data input bit 5. input 50 enc_din6 encoder data input bit 6. input 54 enc_din7 encoder data input bit 7. input decoder control and status pins pin# signal description signal type
COIC5130A specifications co optic ~ ~ 18 encoder data output pins pin# signal description signal type 111 enc_dout0 encoder data output bit 0 tristate 105 enc_dout1 encoder data output bit 1 tristate 97 enc_dout2 encoder data output bit 2 tristate 93 enc_dout3 encoder data output bit 3 tristate 60 enc_dout4 encoder data output bit 4 tristate 68 enc_dout5 encoder data output bit 5 tristate 48 enc_dout6 encoder data output bit 6 tristate 56 enc_dout7 encoder data output bit 7 tristate encoder control and status pins pin# signal description signal type 79 enc_trien tri-states the encoder enc_dout bus drivers when high input 75 enc_enin enable encoder din bus into the parity generator input 73 enc_enout enables encoder din bus onto the dout bus input 71 enc_rdy indicates data symbols are on the encoder enc_dout bus output 77 enc_reset initializes encoder into a know state (high) input 82 enc_clock encoder master and symbol clock. input encoder t select pins pin# signal description signal type 87 enc_ta0 bit 0 of the encoder t select bus input 85 enc_ta1 bit 1 of the encoder t select bus input 83 enc_ta2 bit 2 of the encoder t select bus input 94 enc_ta3 bit 3 of the encoder t select bus input
8v dd +5 v power 17 v dd +5 v power 35 v dd +5 v power 43 v dd +5 v power 49 v dd +5 v power 52 v dd +5 v power 57 v dd +5 v power 66 v dd +5 v power 74 v dd +5 v power 84 v dd +5 v power 89 v dd +5 v power 101 v dd +5 v power 104 v dd +5 v power 114 v dd +5 v power 124 v dd +5 v power 128 v dd +5 v power COIC5130A specifications co optic ~ ~ 19 encoder and decoder foundry test pins pin# signal description signal type 115 dec_test_se foundry test pin - do not use input 51 dec_test_si foundry test pin - do not use input 108 dec_test_so foundry test pin - do not use output 36 enc_test_se foundry test pin - do not use input 45 enc_test_si foundry test pin - do not use input 116 enc_test_so foundry test pin - do not use output ground pins pin# signal description 11 gnd ground 20 gnd ground 23 gnd ground 37 gnd ground 38 gnd ground 47 gnd ground 55 gnd ground 58 gnd ground 69 gnd ground 78 gnd ground 106 gnd ground 109 gnd ground 112 gnd ground 118 gnd ground 126 gnd ground votlage supply pins pin# signal description no connect pins pin# signal description 1 nc no connection 3 nc no connection 5 nc no connection 10 nc no connection 12 nc no connection 14 nc no connection 16 nc no connection 21 nc no connection 26 nc no connection 28 nc no connection 29 nc no connection 31 nc no connection 32 nc no connection 33 nc no connection 34 nc no connection no connect pins, continued pin# signal description 41 nc no connection 62 nc no connection 64 nc no connection 96 nc no connection 98 nc no connection 100 nc no connection 107 nc no connection 121 nc no connection 125 nc no connection 127 nc no connection
COIC5130A specifications co optic ~ ~ 19 packaging table 6: plcc dimensions e3 e1 e index corner pin 1 b e d3 d1 d c q = 0 ?7 a a1 l a2 0.1 g notes: 1. pin 1 indicator may be a corner chamfer, dot or both. 2. controlling dimensions are in millimeters. 3. the top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 4. dimension d1 and e1 do not include mold protrusion. allowable pro- trusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. 6. coplanarity, measured at seating plane g, to be 0.10 mm max. part numbers: complete ordering code COIC5130A parts are packaged in anti static tubes of 18 units each. to order call 650-321-3390, fax 650-322-8569, or email sales@co-optic.com a a1 a2 d d1 d3 e e1 e3 l e b c n nd ne note 128 32 32 square control dimensions in millimeters symbol alternate dimensions in inches min nominal max min nominal max 3.45 0.25 3.20 30.95 27.80 30.95 27.80 0.73 0.30 0.11 4.10 0.50 3.60 31.45 28.20 31.45 28.20 1.03 0.45 0.23 0.136 0.010 0.126 1.219 1.094 1.219 1.094 0.029 0.012 0.004 0.161 0.020 0.142 1.238 1.110 1.238 1.110 0.041 0.018 0.009 24.80 ref. 24.80 ref. 0.976 ref. 0.976 ref. 0.031 bsc. 0.80 bsc. pin features

▲Up To Search▲

Price & Availability of COIC5130A

	To Download COIC5130A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .